1. Field of the Invention
The present invention relates to design testing. In one example, the present invention relates to methods and apparatus for efficiently allowing verification and validation of a design using randomized, self-checking test sequences.
2. Description of Related Art
Verification and validation testing is used to determine that operation of a design is correct, complete, consistent, and meets the requirements of its intended use. A variety of schemes can be used to verify and validate operation of a design. Testing can be performed by using a test plan with a complete set of inputs and a complete set of expected outputs. A test input can be provided to a design under test (DUT), sometimes referred to as a device under test, and the output can be verified using the test plan. However, writing a complete and thorough test plan is often not trivial. It is particularly difficult if a design under test handles numerous inputs and provides numerous outputs simultaneously or if particular inputs provided to the design under test affect processing and alter other expected outputs. Writing a test plan with all of the possible combinations and permutations of inputs can be arduous and error prone. It can also be difficult to determine what error occurred.
Other verification and validation environments rely upon the ability to pass information through a DUT in order to be able to check the results. The information is usually passed unmodified through the data path and even through the control path associated with DUT. The information enables verifying and validating the operation of the DUT. However, including information in test inputs also has limitations. Consequently, it is desirable to provide techniques and mechanisms for improving the ability to providing information through a DUT in order to verify and validate operation of the DUT.